THIS INVENTION relates to the fabrication of a semiconductor structure having quantum wires and, in particular, to a method of fabricating a semiconductor structure having self-organised quantum wires and to a device including such a structure.
It is known that semiconductor devices incorporating quantum structures, such as quantum wires or quantum dots, exhibit enhanced quantum size effects which result in excellent electrical and optical characteristics in comparison with semiconductor devices which have no such quantum structures. For example, when such quantum structures are employed in a laser diode, this may provide advantages such as a low threshold current, a high differential gain, a large modulation bandwidth, a high characteristic temperature and a large non-linear gain.
However, in order to fabricate high quality quantum wires or quantum dots, charge carriers in an active layer must be confined not only in one dimension but in each of two dimensions (in the case of quantum wires) or in each of three dimensions (in the case of quantum dots) by corresponding perfect crystalline interfaces.
There are already a number of known methods for the formation of semiconductor structures having quantum wires.
In one known method, a quantum well is first grown on a semiconductor substrate and lines are lithographically etched in the substrate at intervals of tens of nanometers (nm) using an electron beam or X-rays to define a pattern of wires or dots. The semiconductor is then epitaxially re-grown, using a material with a larger bandgap than the quantum well material, thereby embedding and confining the wires or dots in the larger bandgap material. Quantum wires formed in this manner, however, have many surface irregularities and these greatly reduce the quantum efficiency of the structure.
In another known method, the quantum wires are formed during the growth of an epitaxial layer, for example, by selective growth of an epitaxial layer [Appl. Phys. Lett. 71, 2005 (1997)], by the growth of an epitaxial layer on a micro-patterned substrate [U.S. Pat. No. 5,827,754] or by the growth of an epitaxial layer on a vicinal substrate. For example, U.S. Pat. No. 5,882,952 discloses the fabrication of quantum wires by forming multi-atomic step edges on a (110) surface of a gallium arsenide (GaAs) substrate inclined at an angle toward the [00-1] or the [1-1-1] direction and then growing a gallium arsenide/aluminium gallium arsenide (Ga.As/AlGaAs) double heterostructure on the GaAs substrate to form quantum wires on the steps of the vicinal substrate. U.S. Pat. No. 4,591,889 discloses the formation of quantum wires by growing a submonolayer superlattice on a vicinal substrate parallel to the substrate surface.
Another method of fabricating quantum wires during the growth of an epitaxial layer is by using a horizontal superlattice created by a strain-induced lateral-layer ordering process in molecular beam epitaxy (MBE) [Appl. Phys. Lett. 60, 2892 (1992)] using compounds AC and BC. Here it is confirmed that the growth of an (AC)m/(BC)n short-period superlattice on a substrate, where m and n are the numbers of monolayers and the lattice constants of AC and BC are respectively larger and smaller than that of the substrate, forms a periodic modulation of A-rich and B-rich regions in compound AxB1xe2x88x92x C parallel to the substrate surface which thereby provides lateral confinement of carriers.
The optical and electronic properties of small dimensional semiconductor structures have been improved greatly by the introduction of strain effects. The Stranski-Krastanow (SK) growth mode has been the most important technique in forming quantum dots having unique opto-electronic properties [Phys. Rev. Lett. 73,716 (1994)]. It has been demonstrated that highly strained heteroepitaxial growth generally proceeds by the formation of islands, which can served as quantum dots, after an initial layer-by-layer growth using molecular beam epitaxy (MBE) or metal organic chemical vapour deposition (MOCVD) technology. Studies of these islands by scanning tunnelling microscope (STM) and transmission electron microscope (TEM) have demonstrated that at the initial stage of formation, the islands are dislocation-free and coherently strained to the substrate.
It is an object of the present invention to provide a method of fabricating a semiconductor structure comprising quantum wires which have effective lateral confinement of carriers and exhibit enhanced strain effects and to provide a semiconductor device incorporating such quantum wires.
Accordingly, in one aspect, the present invention provides a method of fabricating a semiconductor structure having self-organised quantum wires, comprising:
a) providing a substrate of a first semiconductor having single atomic steps on a vicinal surface thereof;
b) epitaxially depositing a second semiconductor on the vicinal surface of the substrate, so that the surface of the second semiconductor presents multi-atomic steps;
c) epitaxially depositing on the second semiconductor a third semiconductor which has a larger lattice mismatch than the second semiconductor with the first semiconductor and which has a narrower band gap than the second semiconductor to form quantum wires of the third semiconductor along the edges of the multi-atomic steps of the second semiconductor; and
d) epitaxially depositing on the third semiconductor a fourth semiconductor with a band gap wider than the third semiconductor to bury the quantum wires in the second and fourth semiconductors.
The quantum wires of the third semiconductor are formed spontaneously along the edges of the multi-atomic steps of the second semiconductor after a two-dimensional layer growth of the third semiconductor, the quantum wires having a linear density and a lateral dimension determined by the angle of the vicinal surface and the lattice mismatch between the second and third semiconductors. The layers of the second and fourth semiconductors provide sharp lateral potential steps confining the carriers in each quantum wire.
The result is a semiconductor structure which is reliably formed with uniform quantum wires of predetermined size and density and with enhanced strain effect.
Preferably, the vicinal surface of the substrate is a nominal (001) surface inclined at an angle to the [110] direction and is inclined at an angle of less than ten degrees to the [110] direction.
The second semiconductor is selected to have a lattice mismatch of less than 1.0% with the first semiconductor and, in an embodiment of the invention, the second semiconductor is the same as the first semiconductor.
The fourth semiconductor is chosen to have a lattice mismatch of less than 1.0% with the first semiconductor and, in an embodiment of the invention, the fourth semiconductor is the same as the first semiconductor.
The third semiconductor is selected to have a lattice mismatch of at least 2.5% with the first semiconductor.
The first semiconductor may be any suitable semiconductor, such as GaAs or InP; the second and fourth semiconductors may be selected from the group consisting of compound semiconductors formed from group III and group V elements and compound semiconductors formed from group II and group VI elements; and the third semiconductor may be selected from the group consisting of binary and ternary compound semiconductors formed from group III and group V elements and binary and ternary compound semiconductors formed from group II and group VI elements.
By selecting the semiconductors appropriately, different optical and electronic properties, such as the wavelength of photoluminescence (PL) emission from the quantum wires, can be obtained.
The second, third and fourth semiconductors may be deposited by an epitaxial growth performed by an epitaxial growth technique selected from the group consisting of MOCVD, gas source molecular beam epitaxy (GSMBE), vapour phase epitaxy (VPE), chemical beam epitaxy (CBE) and MBE. In embodiments of the invention, the deposition of the second third and fourth semiconductors is performed by MOCVD.
The second and fourth semiconductors are deposited with a maximum thickness which does not exceed a critical thickness at which dislocations are generated.
The deposition conditions of the third semiconductor on the second semiconductor may be determined by observation of the surface texture using microscopy having resolution on the nanometer scale after the deposition of the third semiconductor. The deposition rate of the third semiconductor should be no more than 2 angstroms (xc3x85) per second (s) and is preferably of the order of 0.1 to 1 xc3x85/s. The third semiconductor may be deposited at a temperature in the range of 380 to 580xc2x0 C., depending on the first semiconductor used. In the case where the first semiconductor is GaAs the deposition temperature of the third semiconductor is preferably in the range of 400 to 550xc2x0 C. The third semiconductor is grown to a thickness of from 0.3 to 3.0 nanometers (nm), such that quantum wires are formed. The thickness of the third semiconductor should not be any thicker, since this may result in the formation of islands and/or dislocations.
A semiconductor structure embodying the invention may be provided with a plurality of layers of quantum wires by repeating steps c) and d) a desired number of times to form a plurality of layers of quantum wires, the thickness of the fourth semiconductor deposited at each stage preferably being no more than 50 nm.
An epilayer with a lattice constant larger than the layer on which it is grown is said to have a positive lattice mismatch. On the other hand, if the lattice constant is smaller than the layer on which it is grown, it is said to have a negative lattice mismatch.
In one embodiment of the invention, the third semiconductor deposited on the second semiconductor has a lattice constant greater than that of the second semiconductor, this positive lattice mismatch placing the third semiconductor under compression. In particular, if the first semiconductor is GaAs, the third semiconductor may, for example, be InAsx Sb1xe2x88x92x (0xe2x89xa6xxe2x89xa61) and the second and fourth semiconductors may be InxGa1xe2x88x92xAs (0xe2x89xa6xxe2x89xa60.2), (thereby forming InAsxSb1xe2x88x92x (0xe2x89xa6xxe2x89xa61) self-organised quantum wires.
In another embodiment, the third semiconductor material deposited on the second semiconductor has a lattice spacing smaller than the second semiconductor, this negative lattice mismatch placing the third semiconductor under tension. In particular, if the first semiconductor is InP, the second and fourth semiconductors may both be InAlAs, which is lattice matched to InP, and the third semiconductor deposited on the second semiconductor may be GaAs, the band gap of which is narrower than that of InAlAs, thereby forming GaAs self-organised quantum wires.
A method embodying the invention thus enables semiconductor structures containing self-organised quantum wires having unique optical and electronic properties to be reliably and controllably fabricated.
In another aspect, the invention accordingly provides a semiconductor device comprising: a substrate of a first semiconductor having single atomic steps on a vicinal surface thereof; a layer of a second semiconductor deposited on the vicinal surface of the substrate and having multi-atomic steps on the surface thereof; a layer of a third semiconductor deposited on the second semiconductor, the third semiconductor having a greater lattice mismatch than the second semiconductor with the first semiconductor and having a narrower band gap than the second semiconductor, the layer of the third semiconductor forming quantum wires along the edges of the multi-atomic steps of the second semiconductor; and a layer of a fourth semiconductor deposited on the third semiconductor, the fourth semiconductor having a wider band gap than the third semiconductor and the quantum wires being buried in the second and fourth semiconductors.
A semiconductor structure embodying the present invention finds particular application as an edge-emitting semiconductor laser.